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PD - 97124D
IRF6710S2TRPbF IRF6710S2TR1PBF
l RoHS Compliant Containing No Lead and Halogen Free Typical values (unless otherwise specified) l Low Profile (<0.7 mm) VDSS VGS RDS(on) RDS(on) l Dual Sided Cooling Compatible l Ultra Low Package Inductance 25V max 20V max 4.5m@ 10V 9.0m@ 4.5V l Optimized for High Frequency Switching Qg tot Qgd Qgs2 Qrr Qoss Vgs(th) l Ideal for CPU Core DC-DC Converters l Optimized for Control FET Application 8.8nC 3.0nC 1.3nC 8.0nC 4.4nC 1.8V l Compatible with existing Surface Mount Techniques l 100% Rg tested
DirectFET Power MOSFET
Applicable DirectFET Outline and Substrate Outline S1 S2 SB M2 M4 L4
S1
L6
DirectFET ISOMETRIC
L8
Description
The IRF6710S2TRPbF combines the latest HEXFET(R) Power MOSFET Silicon technology with the advanced DirectFET TM packaging to achieve improved performance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%. The IRF6710S2TRPbF has low gate resistance and low charge along with ultra low package inductance providing significant reduction in switching losses. The reduced losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors operating at higher frequencies. The IRF6710S2TRPbF has been optimized for the control FET socket of synchronous buck operating from 12 volt bus converters.
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TA = 25C ID @ TA = 70C ID @ TC = 25C IDM EAS IAR
20
Typical R DS (on) (m)
Max.
Units
V
Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Single Pulse Avalanche Energy Avalanche CurrentAg
ID = 12A
g
e e f
h
VGS, Gate-to-Source Voltage (V)
25 20 12 10 37 100 24 10
12 10 8 6 4 2 0 0 4 8 12 16 20 ID= 10A VDS = 20V VDS= 13V
A
mJ A
15 10 TJ = 125C 5 TJ = 25C 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 VGS, Gate-to-Source Voltage (V)
24
QG Total Gate Charge (nC)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
Fig 1. Typical On-Resistance vs. Gate Voltage
Notes:
Click on this section to link to the appropriate technical paper. Click on this section to link to the DirectFET Website. Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple mounted to top (Drain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.49mH, RG = 25, IAS = 10A.
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03/16/10
IRF6710S2TR/TR1PbF
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss RG td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min.
25 --- --- --- 1.4 --- --- --- --- --- 21 --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. Max. Units
--- 17 4.5 9.0 1.8 -7.0 --- --- --- --- --- 8.8 2.3 1.3 3.0 2.2 4.3 4.4 0.3 7.9 20 5.2 6.0 1190 320 150 --- --- --- --- --- --- --- pF VGS = 0V VDS = 13V = 1.0MHz ns --- --- 5.9 11.9 2.4 --- 1.0 150 100 -100 --- 13 --- --- --- --- --- --- nC
Conditions
VGS = 0V, ID = 250A
V mV/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 12A VGS = 4.5V, ID V mV/C A nA S VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 15V, ID =10A VDS = 13V nC VGS = 4.5V ID = 10A See Fig. 15 VDS = 10V, VGS = 0V VDD = 13V, VGS = 4.5VAi ID = 10A RG= 6.2 VDS = VGS, ID = 25A
i = 10A i
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ag Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge --- --- --- --- 14 8.0 1.0 21 12 V ns nC --- --- 100
Min.
---
Typ. Max. Units
--- 19 A
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 10A, VGS = 0V TJ = 25C, IF =10A di/dt = 200A/s
i
i
Notes:
Repetitive rating; pulse width limited by max. junction temperature. Pulse width 400s; duty cycle 2%.
2
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IRF6710S2TR/TR1PbF
Absolute Maximum Ratings
PD @TA = 25C PD @TA = 70C PD @TC = 25C TP TJ TSTG Power Dissipation Power Dissipation Power Dissipation Peak Soldering Temperature Operating Junction and Storage Temperature Range
e e f
Parameter
Max.
1.8 1.3 15 270 -55 to + 175
Units
W
C
Thermal Resistance
RJA RJA RJA RJC RJ-PCB Junction-to-Ambient Junction-to-Ambient Junction-to-Ambient Junction-to-Case Junction-to-PCB Mounted Linear Derating Factor
100
el jl kl fl
Parameter
Typ.
--- 12.5 20 --- 1.0 0.012
Max.
82 --- --- 9.8 ---
Units
C/W
eA
W/C
D = 0.50
Thermal Response ( ZthJA )
0.20
10
0.10 0.05 0.02
R1 R1 J 1 2 R2 R2 R3 R3 C 1 2 3 3
1
0.01
J
Ri (C/W)
(sec)
0.1
Ci= i/Ri Ci= i/Ri
11.759 0.009459 48.48669 0.9378 21.76032 37.2
SINGLE PULSE ( THERMAL RESPONSE )
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc
0.1 1 10 100
0.01 1E-006 1E-005 0.0001 0.001 0.01
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Mounted on minimum footprint full size board with metalized Surface mounted on 1 in. square Cu board, steady state. TC measured with thermocouple incontact with top (Drain) of part. back and with small clip heatsink. R is measured at TJ of approximately 90C. Used double sided cooling, mounting pad with large heatsink.
Notes:
Surface mounted on 1 in. square Cu board (still air).
Mounted on minimum footprint full size board with metalized back and with small clip heatsink. (still air)
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IRF6710S2TR/TR1PbF
1000
TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
1000
TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
10
BOTTOM
100
BOTTOM
1
10
0.1
2.5V
60s PULSE WIDTH
Tj = 25C
2.5V 1
60s PULSE WIDTH
Tj = 175C 10 100
0.01 0.1 1 10 100 VDS , Drain-to-Source Voltage (V)
0.1
1
VDS, Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
1000 2.0
Fig 5. Typical Output Characteristics
ID = 12A
ID, Drain-to-Source Current()
Typical RDS(on) (Normalized)
100 TJ = 175C TJ = 25C TJ = -40C 1
VGS = 4.5V VGS = 10V 1.5
10
1.0
0.1 VDS = 15V 0.01 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 60s PULSE WIDTH
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 6. Typical Transfer Characteristics
10000
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd
Fig 7. Normalized On-Resistance vs. Temperature
30 T J = 25C 25
Typical RDS(on) ( m)
Coss = Cds + Cgd
Vgs = 4.0V Vgs = 4.5V Vgs = 5.0V Vgs = 10V
C, Capacitance(pF)
20 15 10 5
1000
Ciss
Coss
Crss 100 1 10 VDS , Drain-to-Source Voltage (V) 100
0 0 20 40 60 80 100
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
Fig 9. Typical On-Resistance vs. Drain Current and Gate Voltage
ID, Drain Current (A)
4
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IRF6710S2TR/TR1PbF
1000
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on) 1msec
ISD, Reverse Drain Current (A)
100
TJ = 175C TJ = 25C TJ = -40C
100 100sec
10 10msec 1 DC 0.1 TA = 25C Tj = 175C Single Pulse 0.0 0.1 1.0 10.0 100.0
10
1 VGS = 0V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD , Source-to-Drain Voltage (V)
0.01 VDS , Drain-toSource Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
40
VGS(th) Gate threshold Voltage (V)
3.0
Fig 11. Maximum Safe Operating Area
ID, Drain Current (A)
30
2.5
20
2.0
ID = 1.0A ID = 1.0mA ID = 25A
10
1.5
ID = 250A
0 25 50 75 100 125 150 175 TC , Case Temperature (C)
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
TJ , Temperature ( C )
Fig 12. Maximum Drain Current vs. Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
Fig 13. Typical Threshold Voltage vs. Junction Temperature
100
700 Gfs, Forward Transconductance (S) 600 500 400 300 200 100 0 0 20 40 60 80 100 120 140 ID, Drain-to-Source Current (A) VDS = 10V TJ = 25C TJ = 175C
80
ID 1.8A 3.8A BOTTOM 10A
TOP
60
40
20
380s PULSE WIDTH
0 25 50 75 100 125 150 175
Starting TJ, Junction Temperature (C)
Fig 14. Typ. Forward Transconductance vs. Drain Current Fig 15. Maximum Avalanche Energy vs. Drain Current
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IRF6710S2TR/TR1PbF
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Avalanche Current (A)
10
0.01
1
0.05 0.10
0.1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
0.01 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 16. Typical Avalanche Current Vs.Pulsewidth
30
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 10A
20
10
0 25 50 75 100 125 150 175
Starting TJ , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 16, 17: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 19a, 19b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 16, 17). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 17. Maximum Avalanche Energy vs. Temperature
6
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IRF6710S2TR/TR1PbF
Id Vds Vgs
L
0
DUT
20K 1K
S
VCC
Vgs(th)
Qgodr
Qgd
Qgs2 Qgs1
Fig 18a. Gate Charge Test Circuit
Fig 18b. Gate Charge Waveform
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
20V
D.U.T
IAS tp
+ - VDD
A
0.01
I AS
Fig 19b. Unclamped Inductive Waveforms
Fig 19a. Unclamped Inductive Test Circuit
VDS VGS RG
RD
VGS
90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10%
VDS
td(off) tf td(on) tr
Fig 20a. Switching Time Test Circuit
Fig 20b. Switching Time Waveforms
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IRF6710S2TR/TR1PbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * di/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
V DD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 19. Diode Reverse Recovery Test Circuit for N-Channel HEXFET(R) Power MOSFETs
DirectFET Board Footprint, S1 Outline (Small Size Can).
This includes all recommendations for stencil and substrate designs.
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
CL
G = GATE D = DRAIN S = SOURCE
D G D S S
D
D
Optional additional pad to allow interchangeability with S2 outline devices. Mandatory pads to fit S1 outline.
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IRF6710S2TR/TR1PbF
DirectFET Outline Dimension, S1 Outline (Small Size Can).
DIMENSIONS
METRIC MAX CODE MIN 4.85 A 4.75 3.95 B 3.70 2.85 C 2.75 0.45 D 0.35 0.52 E 0.48 0.62 F 0.58 0.52 G 0.48 1.12 H 1.08 N/A J N/A 0.90 K 0.80 1.80 L 1.70 M 0.740 0.68 R 0.020 0.080 0.17 P 0.08 IMPERIAL MIN 0.187 0.146 0.108 0.014 0.019 0.023 0.019 0.042 N/A 0.031 0.066 0.027 0.001 0.003 MAX 0.191 0.156 0.112 0.018 0.020 0.024 0.020 0.044 N/A 0.035 0.070 0.029 0.003 0.007
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DirectFET Part Marking
GATE MARKING LOGO PART NUMBER BATCH NUMBER DATE CODE
Line above the last character of the date code indicates "Lead-Free"
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IRF6710S2TR/TR1PbF
DirectFET Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6710S2TRPBF). For 1000 parts on 7" reel, order IRF6710S2TR1PBF REEL DIMENSIONS STANDARD OPTION (QTY 4800) TR1 OPTION IMPERIAL METRIC METRIC MIN MAX CODE MIN MAX MAX MIN 12.992 A N.C 177.77 N.C 330.0 N.C 0.795 B 19.06 20.2 N.C N.C N.C 0.504 C 0.520 13.5 12.8 13.2 12.8 0.059 D 1.5 1.5 N.C N.C N.C E 3.937 58.72 100.0 N.C N.C N.C N.C F 0.724 N.C N.C 18.4 13.50 G 0.488 11.9 12.4 0.567 14.4 12.01 0.469 H 11.9 11.9 0.606 15.4 12.01 (QTY 1000) IMPERIAL MIN MAX 6.9 N.C 0.75 N.C 0.53 0.50 0.059 N.C 2.31 N.C N.C 0.53 0.47 N.C 0.47 N.C
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING DIMENSIONS IN MM
CODE A B C D E F G H
DIMENSIONS METRIC IMPERIAL MIN MAX MIN MAX 0.311 0.319 7.90 8.10 0.154 0.161 3.90 4.10 0.469 0.484 11.90 12.30 0.215 0.219 5.45 5.55 0.201 0.209 5.10 5.30 0.256 0.264 6.50 6.70 0.059 N.C 1.50 N.C 0.059 0.063 1.50 1.60
Data and specifications subject to change without notice. This product has been designed and qualified to MSL1 rating for the Consumer market. Additional storage requirement details for DirectFET products can be found in application note AN1035 on IRs Web site. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.03/2010
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